The present invention relates to an I2C test single chip for testing an electronic device having an I2C interface.
With the development of high technology, more and more new electronic devices are developed to facilitate our daily life. In order to increase their efficiency and performance, the electronic devices must be organized together and communicable with each other so that different kinds of communication interfaces are developed, such as universal serial bus (USB), inter-integrated circuit bus (I2C), small computer system interface (SCSI), etc.
The I2C bus is a slave-master communication system and is especially suitable for transmitting data from one device to another at a short distance (smaller than 1.5 m). The I2C bus is composed of a serial data line (SDA), a serial clock line (SCL), and a ground line (GND). The electronic devices on the I2C bus are electrically connected to each other by the SDA (11) and the SCL (12), as shown in FIG. 1. In every communication, one device is the master controlling the communication process and one corresponding device is the slave controlled by the master. Simultaneously, one of the aforementioned devices will also be a transmitter for transmitting data and the other is a receiver for receiving data. As shown in FIG. 1, there is a master-receiver device (13) for controlling the slave-transmitter device (14) to send out data so that the master-receiver device (13) can receive data from the slave-transmitter device (14).
After an electronic device is assembled, all parts of the electronic device need to be tested for obtaining high-quality control. The methods for testing an electronic device with or without an I2C interface are very different. For an electronic device (21) without an I2C interface, the electronic device (21) is only connected to a test system (22) which is used for providing an AC current and various kinds of I/O test signals, such as an overload signal, a short-circuit signal, or an overheat signal, as shown in FIG. 2. For an electronic device (21) with an I2C interface, the electronic device (21) is connected to an AC source (31), an electronic load (32), and an I2C test machine (33) respectively, as shown in FIG. 3. The AC source (31) is used for providing an AC current for the electronic device (21), the electronic load (32) is used for providing I/O test signals, such as short-circuit signal and overload signal, and the I2C test machine (33) is used for testing the I2C interface of the electronic device (21). The I2C test machine (33) is usually a computer having an I2C interface and a test program written by C language for processing the I2C test procedures.
To write an I2C test program needs to combine the knowledge of interface control, control commands, program language, the functional requirements of the electronic device, and related software and hardware. Therefore, it is very difficult to write a good test program. Even though a test program is written, it is very hard to maintain such a complicated program. Consequently, using a test machine or computer to test the I2C interface is very inconvenient.
It is therefore attempted by the applicant to deal with the above situation encountered with the prior art.
An object of the present invention is to provide an I2C test single chip for testing the I2C interface of an electronic device.
The I2C test single chip is electrically connected to a test-environment-providing system and the electronic device. The test-environment-providing system is used for outputting a test signal to an electronic device having an I2C interface and outputting a second signal to said I2C test single chip simultaneously.
The I2C test single chip includes a first interface, a second interface and a chip body. The first interface is also an I2C interface and is electrically connected to the I2C interface of the electronic device for receiving a first signal from the I2C interface of the electronic device in response to the test signal. The second interface is electrically connected to the test-environment-providing system for receiving the second signal. The chip body is used for taking a processing procedure to assist the test-environment-providing system in testing the electronic device in response to the first signal and the second signal.
According to the present invention, the chip body includes a memory unit, a control unit, and a responding unit. The memory unit is used for recording a corresponding rule between the first signal and the second signal when the I2C interface of the electronic device is well-functioned. The control unit is electrically connected to the memory unit for finishing the processing procedure according to the corresponding rule. The responding unit is electrically connected to the control unit for taking a responding procedure after the control unit finishes the processing procedure.
Preferably, the control unit is a comparator or a microprocessor.
In accordance with the present invention, the processing procedure is to compare a received relationship between the first and the second signals with the corresponding rule to check whether the received relationship between the first and the second signals is correct and to output a test result to the responding unit.
According to the present invention, if the responding unit is a displaying device, such as a liquid crystal display (LCD) monitor, the responding procedure is to display the test result on the displaying device.
According to the present invention, if the responding unit is a responding circuitry, the responding procedure is to output the test result back to the test system.
Preferably, the memory unit is a read-only-memory (ROM).
Preferably, the electronic device is a server power supply.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which: